Library Declaration:
A library is a collection of codes which can be used by several other functions.
Structure of library declaration is given below:
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
The above code can be used for all VHDL code.
Entity:
Entity defines all the input and output ports of the circuit.
Example:
Suppose a full adder circuit which has three inputs and two outputs. So ENTITY declaration of fulladder can be written in the following way.
Suppose a full adder circuit which has three inputs and two outputs. So ENTITY declaration of fulladder can be written in the following way.
Entity full_adder is --full_adder is the name of the entity
Port( Ain: in std_logic; --Port Ain to Port Cout declaration
Bin: in std_logic;
Cin: in std_logic;
Sum: out std_logic;
Cout: out std_logic);
End full_adder;